Hardware-accelerated path planning
A Hybrid A* path planner for autonomous driving, synthesised from C++ for an FPGA. Here it runs as WebAssembly.
Open the labAI researcher & engineer · London

PhD researcher
King’s College London · DRIVE-HealthGenerative sequence models for healthcare. Previously software development engineer at Amazon Web Services.
A Hybrid A* path planner for autonomous driving, synthesised from C++ for an FPGA. Here it runs as WebAssembly.
Open the labECoProNAS, a NAS technique that halves the GPU time needed to search a cell architecture.
Saved PULSE CNF checkpoint outputs from synthetic, non-patient histories. Enable JavaScript to explore a model trained on CVSim-style data in three saved scenarios.
PULSE, a probabilistic simulator family for intensive-care EHR trajectories.
Try the app A questionnaire-led prototype for exploring personal priorities and possible actions.
Background
Oct 2017–Mar 2021 · Software engineer · dual student
Web and database integrations, C# applications and hardware-accelerated autonomous-driving path planning.
The path plannerFeb 2023–Sep 2025 · Software development engineer
Core hypervisor and CPU-platform work, including Linux kernel backports and assembly/register-level debugging.
Oct 2025–present · PhD researcher
Generative sequence models for healthcare in the EPSRC DRIVE-Health programme, supervised by Angus Roberts and Julia Ive.
PULSE